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Dual Low-Drop Voltage Regulator
TLE 4476 GM
Target Data
Features * * * * * * * * * * * Output 1: 250 mA; 3.3 V 4 % Output 2: 330 mA; 5.0 V 4 % Enable input for output 2 Low quiescent current in OFF state Wide operation range: up to 42 V Reverse battery protection: up to 42V Output protected against short circuit Wide temperature range: - 40 C to 170 C Over-voltage protection up to 65 V (< 400 ms) Over-temperature protection Over-load protection
P-TO252-5-1 (D-PAK)
Type
w TLE 4476 GM w New type
Ordering Code Q67006-A9362
Package P-TO252-5-1 (D-PAK) (SMD)
Functional Description The TLE 4476 is a monolithic integrated voltage regulator providing two output voltages, output Q1 is a 3.3 V output for loads up to 250 mA and output Q2 is a 5 V output providing 330 mA. The device is available in the P-TO252-5-1 (D-PAK) package. Output 2 can be switched ON / OFF via the Enable input. The TLE 4476 is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against over load, short circuit and over temperature.
Semiconductor Group
1
1998-11-01
TLE 4476 GM
Pin Configuration (top view)
GND
1 Q1 Q2 EN
5
AEP02562
Figure 1 Pin Definitions and Functions Pin No. 1 2 3 4 5 Symbol I Q1 GND Q2 EN Function Input voltage; block to GND directly at the IC with a ceramic capacitor 3.3 V output; block to GND with a capacitor CQ1 10 F, ESR < 10 at 10 kHz Ground 5.0 V output; block to GND with a capacitor CQ2 10 F, ESR < 5 at 10 kHz Enable input; to switch ON and OFF Q2, ON with high signal
Semiconductor Group
2
1998-11-01
TLE 4476 GM
1
2
Q1
Bandgap Reference
4
Q2
EN
5
3 GND
AEB02563
Figure 2 Block Diagram
Semiconductor Group 3 1998-11-01
TLE 4476 GM
Absolute Maximum Ratings - 40 C < Tj < 170 C Parameter Symbol Limit Values Unit min. Input I Voltage Current 3.3 V Output Q1 Voltage Current 5.5 V Output Q2 Voltage Current Inhibit EN Voltage Current Temperatures Junction temperature Storage temperature max. Remarks
VI II
- 42 - -
42 65 -
V V mA
-
t < 400 ms
Internally limited
VQ1 IQ1
-1 -
36 -
V mA
- Internally limited
VQ2 IQ2
-1 -
36 -
V mA
- Internally limited
VEN IEN
- 42 - -
42 65 -
V V mA
- t < 400 ms Internally limited
Tj Tstg
- 50 - 50
170 150
C C
- -
Note: ESD-Protection according to MIL Std. 883: 2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
4
1998-11-01
TLE 4476 GM
Operating Range Parameter Output 1 input voltage Output 2 input voltage 3.3 V regulator output current 5.5 V regulator output current Junction temperature Thermal Resistances Junction case Junction ambient Symbol Limit Values min. max. 42 42 250 330 170 V V mA mA C - - - - - 4.5 5.7 0 0 - 40 Unit Remarks
VI1 VI1 IO1 IO2 Tj
Rth,j-case Rth,j-a
- -
5 65
K/W K/W
- -
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
5
1998-11-01
TLE 4476 GM
Electrical Characteristics
VI = 13.5 V; VEN > VENH ; - 40 C < Tj < 150 C; unless otherwise specified
Parameter Symbol Limit Values min. typ. 3.3 V Output Q1 Output voltage Output current limitation Output drop voltage; VDRQ1 = VI - VQ1 Load regulation Line regulation max. Unit Test Condition
VQ1 IQ1 VDRQ1
3.17 250 -
3.3 - 0.7
3.43 - 1.2
V mA V
1 mA < IQ1 < 250 mA see note 1
IQ1 = 250 mA; see note 1
VQ1 VQ1
- - - 10 -
- - 60 - -
30 30 - - 10
mV mV dB F
1 mA < IQ1 < 250 mA IQ1 = 5 mA; 6 V < VI < 28 V 20 Hz < fr < 20 kHz; Vr = 5 VSS - at 10 kHz
Power-Supply-Ripple- PSRR Rejection Value of output capacitance ESR of output capacitance 5.0 V Output Q2 Output voltage Output current limitation Output drop voltage; VDRQ2 = VI - VQ2 Load regulation Line regulation
CQ1 RESRQ1
VQ2 IQ2 VDRQ2
4.8 330 -
5.0 - 0.4
5.2 - 0.7
V mA V
1 mA < IQ2 < 330 mA see note 1
IQ2 = 330 mA; see note 1
VQ2 VQ2
- - -
- - 60
50 50 -
mV mV dB
5 mA < IQ2 < 330 mA; IQ2 = 5 mA; 6 V < VI < 28 V 20 Hz < fr < 20 kHz; Vr = 5 VSS
Power-Supply-Ripple- PSRR Rejection
Semiconductor Group
6
1998-11-01
TLE 4476 GM
Electrical Characteristics (cont'd)
VI = 13.5 V; VEN > VENH ; - 40 C < Tj < 150 C; unless otherwise specified
Parameter Value of output capacitance ESR of output capacitance Current Consumption Quiescent current; Iq = II - IQ1 Quiescent current; Iq = II - IQ1- IQ2 Quiescent current Iq = II - IQ1 Quiescent current Iq = II - IQ2 Enable input EN ON voltage treshold Symbol Limit Values min. typ. max. - 10 F - at 10 kHz 10 - - - Unit Test Condition
CQ2 RESRQ2
Iq Iq Iq Iq
- - - -
100 150 - -
- - 10 15
A A mA mA
Tj < 85 C VEN < VENL
IQ1 = IQ2 = 300 A; Tj < 85 C IQ1 = 150 mA, IQ2 = 300 A IQ1 = 300 A, IQ2 = 250 mA,
VENH OFF voltage treshold VENL input current VEN
- 1.0 -
1.4 1.3 20
1.8 - -
V V A
VQ1 or 2 > 4.9 V VQ1 or 2 < 0.1 V VEN = 13.5 V
Note 1: Measured when the output voltage VQ has dropped 100 mV from the nominal value.
Semiconductor Group
7
1998-11-01
TLE 4476 GM
Application Information
4.5 - 42 V
1
2 Q1
3.3 V
C 470 nF
C Q1 22 F
Bandgap Reference
4 Q2
5V
C Q2 22 F
e.g. from Ignition
EN 5
3 GND
AES02564
Figure 3 Application Circuit Input, Output The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 in series with CI, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors CQ1 and CQ2 are necessary. Stability is guaranteed at values CQ1 10 F (ESR 10 ) and CQ2 10 F (ESR 10 ) within the operating temperature range. Enable By the enable feature the output 2 (5V output) can be switched ON or OFF. The enable input can be connected directly to terminl 30 (battery line) or 15 (ignition line). Of course its also possible to conrol the output 2 via the microcontroller.
Semiconductor Group
8
1998-11-01
TLE 4476 GM
Package Outlines P-TO252-5-1 (D-PAK) (Plastic Transistor Single Outline)
6.5 +0.15 -0.10
2.3 +0.05 -0.10 B A 1 0.1 0...0.15 0.9 +0.08 -0.04
1 0.1
5.4 0.1
9.9 0.5 6.22 -0.2
0.8 0.15
(4.17)
0.15 max per side
0.51 min
5x0.6 0.1 1.14
0.5 +0.08 -0.04 0.1
4.56
0.25
M
AB
GPT09161
All metal surfaces tin plated, except area of cut.
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 9
Dimensions in mm 1998-11-01

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